A 100dB SNR 2.5MS/s output data rate /spl Delta//spl Sigma/ ADC

A multi-bit cascaded 2-2-0 /spl Delta//spl Sigma/ modulator in 0.25/spl mu/m CMOS attains 100dB SNR in a 1MHz signal bandwidth. The complete A/D converter includes an on-chip operational amplifier for driving the large input capacitors dictated by kT/C noise, a reference buffer and a programmable decimation filter. The power consumption of the modulator including reference buffer is 475mW from a dual supply (2.5V and 5V).