Low voltage techniques for sub 100nm CMOS, RF transceivers

Sub 100 nm CMOS provides high f/sub T/ and f/sub max/ devices that offer many advantages for RFIC design. However, these benefits come with the necessity of using low supply voltages (/spl sim/1.2 V) and low resistivity substrates. In this paper, we describe circuit techniques for WLAN components (LNAs, synthesizers, filters and ADC front ends) that overcome these constraints while fully realizing the advantages of scaled CMOS.