Evaluation of self-heating effects on an innovative SOI technology ("Venezia" process)

In this paper we investigate the thermal resistance associated to a power DMOS device realized by means of an innovative SOI process (Venezia process). First we present a simple experimental technique enabling to characterize device thermal transient by looking at its related drain current waveform, then we analyze and discuss the obtained experimental results pointing out the difference in thermal resistance between Venezia buried oxide and the one manufactured by standard technology.