Multilevel differential encoding with precentering for high-speed parallel link transceiver

A multilevel differential encoding scheme is proposed as a new approach for use in high-speed parallel transceiver systems. While incurring little or no increase in the number of links, the proposed encoding scheme overcomes two major problems in single-ended parallel links-reference ambiguity and power-line fluctuations. The proposed scheme transmits differentially encoded data among the pins and adjusts the driving current to be constant so as to minimize the L(di/dt) switching noise on the output driver power lines. A new precentering scheme is also applied to maximize the horizontal eye opening by centering all signals during a predefined time before the start of the next symbol transition. To verify the proposed schemes, a transceiver chip was designed and fabricated in 0.25-/spl mu/m CMOS technology. The chip, which consists of 18 parallel links with only three ground and three supply pins for the output drivers, employs a three-level differential encoding scheme to achieve a maximum data rate of 1.8 Gb/s with a bit error rate of less than 10/sup -12/.