Source—Drain contact resistance in CMOS with self-aligned TiSi2

The contact resistance between TiSi
2
and n
⁺
-p
⁺
source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10
^-7
and 1 × 10
^-6
Ω . cm
²
can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10
²⁰
/cm
³
. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi
2
-n
⁺
and TiSi
2
-P
⁺
interfaces.