The scaling law of alpha-particle induced soft errors for VLSI's

The scaling law of alpha-particle induced soft errors for VLSIs is investigated using a 3-D device simulator and experimentation. In it, effective funneling length(L
F
), which is different from Hu's model, is proposed as a guideline for submicron cell/ device design. Effective funneling length was found to strongly depend on a memory cell size(pn-junction size)--"size effect", and a cell space--"proximity effect", as well as substrate impurity concentration. These results were also proven by experimental results. A new experimental method used here makes a good use of only one-bit cell with actual dimen tions and is very useful for determination of soft-error-rate(SER) and feasibility check of many candidates for mega-bit memory cells. Thus, based on these new findings of funneling phenomena, proposed simulation and experimental methods, it was found that a kind of scaling law for alpha-particle induced soft errors exists which determines the limitation of planar cells, stacked capacitor cells, and trench cells.