Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions. The validity of these published expressions has not been verified so far for small-geometry devices of different parameters. Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature. In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current. Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values. Hence we determined a set of new geometry parameters η and
B/A
for the DIBL threshold relationship that can be used with the analytical model. Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required. Also, our results should be useful for calibrating existing analytical MOSFET models. In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices.