A dual buried layer technology for the fabrication of high voltage NPN devices compatible with a 1.5 micron epitaxial bipolar process

This paper presents a technique to integrate an optional high voltage high speed NPN transistor in a low voltage (LV) LSI bipolar process. The design approach of the LV process maximizes the device speed by forming a very narrow base width (0.15µm) and a heavily doped buried layer (ρs=20Ω/□). LSI capability is achieved by using recessed oxide isolation on a 1.5µm thick epitaxial layer. This process architecture tends to limit LV
CEO
and BV
CBO
to about 10 and 20 volts respectively. The voltage capability can be expanded, however, without affecting the primary specifications of the LV process. This is achieved by the addition of a lightly doped buried layer. The feasibility of this concept is demonstrated by solving the Poisson equation. A high voltage (HV) device with a minimum LV
CEO
of 45 volts and f
T
of 1.2 Ghz has been fabricated. The narrow base width is sufficient to keep the HV device from punch through. Experimental results for a range of doping profiles are presented.