Application of the lamp-annealing method to the n+-layer of WSix-gate self-aligned GaAs MESFET's

The electrical properties of the Si-implanted n+-layer and the WSi
x
/n-GaAs Schottky contacts were investigated after lamp annealing at temperatures up to 1050°C in order to apply the lamp-annealing method to the source-drain n+-layer of WSi
x
-gate self-aligned GaAs MESFET's. Experimental results show that WSi
x
/n-GaAs Schottky contacts are not subjected to interfacial degradation at temperatures required for fully activating the n+-implanted dopant. It is demonstrated that this method is effective in improving FET performance at short gate lengths of 1.0 µm. About a 50- percent improvement in K-value was achieved compared to conventional furnace-annealed FET's. It is implied that this improvement is due to reduced short-channel effects.