High-density and reduced latchup susceptibility CMOS technology for VLSI

Increasing layout density and reducing susceptibility to latchup are two of the most pressing concerns in making CMOS a superior VLSI technology. This work presents a possible solution to these CMOS issues. Significant reductions of the well (in our case p-well) resistance and of the well side diffusion are the results of the incorporation of a heavily doped epitaxial buried layer in the CMOS process. Using this approach n
⁺
-p
⁺
spacings of 3.5 µm give adequate punchthrough margin for 5-V operation and, compared to a conventional CMOS process, a sevenfold improvement in holding current.