Shallow p-wells for fine dimension CMOS circuits

This paper examines the feasibility of using very shallow p-wells, with depths as low as 0.8 µm, for CMOS devices. Such wells will be essential if the full potential of fine dimension CMOS circuits, with minimum linewidths in the 1-1.5-µm range, is to be realized. A preliminary study of simple breakdown phenomena reveals a limited range of total well doses that axe potentially suitable. The properties of n-channel transistors and simple CMOS circuits utilizing these wells, are extensively studied. Excellent short n-channel characteristics are obtained without the need for any additional channel implants. Successful operation of CMOS inverters and ring oscillators based on 1-µm and 1.5-µm gate length transistors, with supply voltages up to 10 V, is demonstrated and the latchup susceptibility of the structures is outlined. The advantages of using the minimum well doping are illustrated, and no degradation of device or circuit performance even in the shallowest wells is observed.