A large V/sub DS/ data retention test pattern for DRAM's

A test pattern for testing DRAM cell data retention that differs from conventional retention time tests is described. The test pattern is applicable to non-V/sub DD/ bit-line precharge designs, and is specifically designed to test for worst-case subthreshold leakage through the cell access device by holding bit lines in their latched position for extended periods. This action stresses the cell access devices with the worst-case V/sub DS/ across them. The reasons to perform this test on a DRAM are reviewed, its advantages over standard retention time tests are described, and its ability to differentiate access device leakage from isolation leakage is discussed. Measured results on a 1-Mb chip are shown, illustrating the test pattern's effectiveness in screening subthreshold leakage.<
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