Performance comparison of highly integrated circuits: Silicon NMOS versus gallium arsenide normally-off MESFET technology

This study presents a performance comparison between highly integrated circuits on gallium arsenide and on silicon realized with normally-off MESFET's and n-channel MOSFET's, respectively. As a basis, a standard cell structure is chosen in order to obtain a realistic capacitive loading. This cell is scaled down twice from an area of 1 mm
²
to 0.38 mm
²
and to 0.13 mm
²
. The corresponding effective gate length inside the cell is 1, 0.5, and 0.2 µm, respectively. The delay time of a loaded inverter, the power consumption as well as the power-delay product are calculated using device parameters deduced from experimental
I-V
characteristics. For MOSFET's good noise margins at low switching times are obtained at a supply voltage of 3 V. The GaAs circuit exhibits a lower power consumption by one order of magnitude and a smaller delay time by about a factor of 2. Since nonoptimized GaAs MESFET's with recessed gates were regarded for the comparison improvements are expected for self-aligned MESFET's. For a supply voltage of 1 V, the MOSFET circuit shows a comparable power consumption to the GaAs circuit but longer delay time (factor 2 to 5).