Study of the input and reverse transfer capacitance of vertical MOS transistors

The input capacitance of vertical MOS transistors shows, when it is measured in the current flow state, much higher values than in the currentless state (
V_{GS} = 0
). This can partly be attributed to the Miller-effect with the internal drain series resistance of the epitaxial layer working as a load resistance. Moreover there is an additional increase of the reverse transfer capacitance by more than an order of magnitude because of accumulation beneath the gate. This effect more or less depends on the current according to the epi-doping, and it occurs especially on transition from the linear to the pentode region. Measurements of the input and computed values of the reverse tranfer capacitance and its dependence on current will be presented for transistors with different dopings and heights of the epitaxial layer.