Reduced geometry CMOS technology

In this presentation, the authors review bulk silicon CMOS evolution and discuss the suitability of scaling CMOS to one micron features. Characterization data from one micron twin-tub processes fabricated on both n and p-type starting material will be reviewed. These data include latch-up sensitivity of the technology in which the dramatic improvement achievable with retrograde implantation will be highlighted. The outstanding performance achievable with reduced geometry will be emphasized with data obtained from a dual modulus prescaler which has operated at clock rates in excess of 1 Ghz at 5 volts.