Considerations for scaled CMOS source/drains

In scaling CMOS below 2 µm patterned gate length, the higher diffusivity of boron (p-channel source/drain) than of arsenic (n-channel source/drain) requires a departure from NMOS device technology. Consideration of p-channel threshold control and subthreshold current suppression limit p+ S/D implant dose to almost a factor of 10 below the 10
¹⁶
/cm
²
arsenic limit for n+ S/D. This raises the possibility of performing the boron S/D as an unmasked implant to save one masking step. It is shown that the n-channel device with S/D background doped by an unmasked 10
¹⁵
cm
^-2
boron implant has insignificant shift in threshold voltage and only very little increase in standard deviation of threshold voltage as compared to control n-channel devices. The increased resistivity resulting from a lower implant dose, however, essentially eliminates it from use as an interconnect layer. A self-aligned silicide layer formed on the source/drains is discussed as an enhancement to correct this deficiency.