Some device aspects of the epitaxial collector IIL/MTL technology

Device aspects of the epitaxial collector IIL/MTL configuration incorporating Schottky-barrier junctions (SBJ's) as output contacts (Schottky coupled IIL or Schottky coupled transistor logic) and V-grooves as lateral isolation is discussed. Typical figures for single output gates are a power-delay product of 0.10-0.18 pJ and a minimum propagation delay of 3.5-5 ns with 5- 7.5-µm design rules. Using shallow epitaxy and a reduced effective temperature of the high temperature processing steps, a 1-ns speed operation is predicted with a 4-µm feature size, thus approaching other advanced bipolar logic performances, while maintaining IIL power economy, gate density, and layouting flexibility.