1 GHz GaAs CCD

Sampled analog processing techniques when implemented with CCDs are well suited to application in filtering, correlation, convolution, etc. The existing silicon technology has not, however, been effectively applied to these functions at very high sample rates (
\geq 10^{9}
samples/sec). Difficulties have been experienced in the high speed operation of silicon CCDs. Most notably, clock driver power dissipation, bandwidth of on-chip amplifiers and low-field electron mobility have limited useful performance of silicon CCDs to about 100 MHz. A new CCD technology in GaAs, first introduced in 1977, has been developed to the point where reasonably long devices (400 gates) and extremely high clock frequencies have been achieved. These CCDs are buried channel and employ Schottky barrier gates separated by small (
\cong 1 \micro
m) gaps. Operated in the conventional manner, charge transfer efficiencies of >0.9999 per transfer have been measured. The charge transfer efficiency does not degrade beyond 100 MHz. At higher frequencies, a considerable measurement problem exists in determining the charge transfer efficiency. Of course conventional clocking schemes are not applicable at RF frequencies. A novel approach to very high speed clocking of CCDs has been employed and will be discussed. The GaAs CCD has very recently been continuously clocked at ≥ 1 GHz. The maximum clock frequency achieved to date is limited by the clock driver system. This CCD is predicted to operate at up to 5 GHz. The device technology used to fabricate the GaAs CCD, the measurement techniques and the latest results as well as applications will be discussed.