Performance limitations of silicon bipolar transistors

As the very large-scale integration (VLSI) era begins, the limitations to improving integration in silicon semiconductor technology are being studied, and the integration of many millions of components per single integrated circuit chip is predicted. In this paper we consider some performance limitations of silicon bipolar transistors, assuming our ability to fabricate small geometric devices, by device analysis using an accurate two-dimensional numerical solution of classic semiconductor transport equations. The applicability of mathematical equations used to represent carrier transport in small geometric bipolar transistors and silicon-material parameters, such as bandgap narrowing with doping, ionization coefficients, and lifetime, used in the model has also been considered. The terminal characteristics, the internal behavior, and performance limitations due to voltage and current operating levels of bipolar transistors with emitter depths and basewidths ranging from 0.4 µm to 30 nm have been analyzed. The results of our calculations indicate that the f
T
and
f_{\max}
of a bipolar transistor of 1 × 1 µm
²
emitter size, 30 nm emitter depth, and 30 nm basewidth are about 89 and 6.1 GHz, respectively, at 0.73 mA collector current. Maximum V
BC
before base-collector junction breakdown at this current level is -2 V. For a device of 1 × 1 µm
²
emitter size, 100 nm emitter depth, and 100 nm basewidth, the calculated values of f
T
and
f_{\max}
are 16.8 and 9.9 GHz, respectively, at a collector current of 0.38 mA.