The use of a silicon-gate C-MOS/SOS test vehicle to evaluate technology maturity

This paper describes a comprehensive test vehicle that has been used to characterize the silicon-gate C-MOS/SOS technology. Specifically, it has facilitated the verification of a set of topological layout rules and mask sequence which are producible industry-wide; the establishment of electrical design parameters; and has provided information on the present yield and performance range of the technology. In addition, structures included on the vehicle make it suitable for process development.