Some characteristics of nonvolatile CdSe thin-film memory transistors

Improvement on CdSe thin-film memory transistors was made by optimizing the deposition condition of aluminum interfacial dopant (IFD) between the two dielectric insulators of the gate. Threshold voltage window of the devices was optimized at IFD thickness of about 10 to 20 Å and was found to increase with IFD deposition rate. Charging speed of the optimized devices was improved by an order of magnitude over previously unoptimized devices.