4096-Bit serial decoded multiphase serial-parallel-serial CCD memory

A new practical form of charge-coupled device (CCD) memory structure is described which achieves high storage density while providing low clock-line capacitance. In the new structure, the time-division multiplexing of multiphase concepts is replaced by the spatial multiplexing of a serial-parallel-serial (SPS) array. By using a ring counter to generate the multiphase clocking, a compact method of clock generation is described which allows the integration of multiphase drivers into the memory array. The improved density results from using a multiphase technique while the low clock-line capacitance stems from integrating the necessary drivers into the memory structure. The average bit density of the new structure including all necessary drivers exceeds that of previously discussed CCD memory structures when similar layout rules and gate electrode configurations are applied. A 4096-bit memory chip was built to fully demonstrate the new multiphase serial-parallel-serial storage (MSPS). The memory chip additionally uses serial decoding to increase the ratio of bit storage area to decoding circuitry area. The memory chip performed all memory functions of READ, WRITE, and REFRESH. The memory is organized into 16 separate 256-bit CCD shift registers. It is also found that interlacing is effective in increasing the average bit density in MSPS structures. The combination of high density and low drive capacitance makes the MSPS structure appear attractive for memory applications.