I2L II

Present I
²
L devices are limited in usable speed and current gain by the low performance of the inverse NPN transistor made with conventional bipolar processes. This report discusses new I
²
L structure variations that overcome these limitations. In addition, a new process is described where the intended isolation regions are anodized to form a conduction barrier. This new I
²
L II Process has already yielded NPN transistors with h
FE
= 250 and f
T
= 250MHz and is expected to extend I
²
L further into the high end of the speed power curve with f
T
> 500MHz and propagation delays of 5ns.