Self-aligned maskless chan stops for IGFET integrated circuits

Many IGFET integrated circuits incorporate a region of enhanced doping under the field oxide to eliminate the possibility of spurious inversion layers causing leakage between devices. Using chemical predeposition technology, this typically requires a photolithographic step to define the region of enhanced doping. This paper describes a structure in which a nonselective implantation that forms an enhanced doping over the entire wafer is selectively compensated through windows patterned in the field oxide to form gate oxide regions. Threshold voltage control is excellent and identical to control devices fabricated without chan stops. The channel hole mobility is normal and no undesirable effects have been observed if care is exercised in controlling the implanted doses. MOS characteristics are normal and are not affected by residual ion damage. Typical parameters for p-channel devices are shown for various levels of compensation, resulting in gate threshold voltages ranging from -0.5 →-2.2 V for p-channel devices. The field threshold is -18.V for a 7000 Å thick field oxide and hole mobilities range from 190 to 290 cm
²
/V.s.