Computer analysis of the double-diffused MOS transistor for integrated circuits

The effective length of an MOS transistor can be made narrow by using double diffusion similar to a bipolar transistor. Computations were conducted for an n-channel double-diffused transistor with different surface concentrations, channel lengths, channel gradients, surface-states densities, and substrate concentrations. A shorter channel length and a higher surface-state density, e.g.
\langle1, 1, 1\rangle
crystal, gave a higher drain current and transconductance. The maximum transconductance in many cases occurs at low gate voltages. The computations indicate that a gain-bandwidth product in the gigahertz range can be expected when the graded channel region is less than 1 µm. The difference between an n-type substrate and a p-type substrate is not substantial. The analysis is also useful in predicting the performance of any integrated logic circuit using the diffused enhancement transistor as the active switch and a depletion-mode transistor (without a diffused channel) as the load device. The computation indicates that satisfactory performance can be obtained using a load device with the same geometry and an ON voltage of only a fraction of a volt, This revelation indicates that double-diffused channel MOS transistors not only give higher speed but also smaller chip area for integrated circuits and a lower supply voltage (hence less power dissipation).