Zigzag super cut-off CMOS (ZSCCMOS) scheme with self-saturated virtual power lines for subthreshold-leakage-suppressed sub-1-V-VDDLSI's

A new Zigzag Super-Cut-off CMOS (ZSCCMOS) is proposed, where only low-V
TH
switches are used so that the ZSCCMOS can be extended to sub-1-V V
DD
region. A zigzagging configuration with self-saturated virtual power lines can eliminate the necessity of series-connected cut-off switches of the SCCMOS without introducing the high-voltage stress problem. In the 70-nm technology node, the ZSCCMOS is expected to reduce a leakage current to the 1-pA-order per gate from the 10-nA-order per gate, achieving the 20-60% faster active-mode speed and the 11 times faster standby-to-active recovery time than the SCCMOS when V
DD
=0.6 V.