A 500MHz supply noise insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter

A 500MHz supply noise insensitive CMOS PLL with a voltage regulator using a capacitive DC-DC converter (VRCC) achieves a jitter level of 30ps rms for quiet supply, and 42ps rms for 600mV supply noise, with a locking range of 110MHz to 850MHz. The worst case PSNR using VRCC shows -45dB in the medium frequency. The circuit is fabricated in a 0.35µm, 3.3V standard digital CMOS process and occupies 2.2mm
²
. The power consumption at 3.3V including buffer is 42mW at 500MHz.