An 8-bit 13-Msamples/s digital-background-calibrated algorithmic ADC

An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit 2-stage pipelined algorithmic analog-to-digital converter. At a sampling rate of 13 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic range (SFDR) is 60 dB. The total power dissipation is 23 mW from 3.0V. The active analog area is 0.11 mm
²
. The digital calibration is implemented off chip.