A low-power 14-b 5 MS/s CMOS pipeline ADC with background analog self-calibration

This paper presents a low-power 14-b 5 MS/s area-optimized pipelined ADC with background analog self-calibration. Measured results from the prototypes fabricated in a 0.6 µm 5 V DPDM CMOS technology show 13.5-b DNL, 12-b INL, 80 dB SFDR and 76 dB SNDR. The core area is 10mm
²
and it dissipates less than 145mW at 5V.