A two-bit Δ Σ-modulator with 83dB SNDR for digital cellular telephones

The design of a two-bit 2nd order ΔΣ-modulator with 83.3dB peak SNDR and 52MHz sampling frequency is presented. The modulator employs a two-bit internal quantization to reduce the slewing requirements of the amplifiers. The nonlinearity of the internal multibit DACs is reduced with dynamic element matching. Both cyclic and random selection algorithms were implemented for comparison purposes. The modulator operates on a 2.7V supply voltage, consumes 23mW power and is targeted for radio receivers with digital channel selection.