A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications

The design of a high-resolution high-speed delta-sigma analog-to-digital converter that operates from a single 3.3V supply is presented. This supply voltage presents several design problems, such as the reduced signal swing and the non-zero switch-resistance in the switched-capacitor circuits. These problems are tackled in this design without the use of special circuit techniques, such as clock-boosters. The converter uses a 2-1-1 cascade topology with optimised coefficients. For an oversampling-ratio of only 24, the converter achieves a SNR of 87 dB, a SNDR of 82 dB and an input dynamic range of 15 bits after comb-filtering. The converter is sampled at 52.8 MHz, which results in the required signal bandwidth for ADSL-applications of 1.1 MHz. It is implemented in a 0.5 µm CMOS technology, in a 5 mm
²
die-area and it consumes 200 mW from a 3.3 V power supply.