0.5 V asymmetric three-Tr. cell (ATC) DRAM using 90nm generic CMOS logic process

Asymmetric three-Tr. cell (ATC) DRAM which has one P-and two N-MOS transistors for one unit cell is proposed with "forced feedback sense amplifier" and "write echo refresh". Memory array of ATC DRAM operates at 0.5V and use only logic process with no additional process. A test chip on 90 nm technology dissipates 180 /spl mu/A in refresh current at 1 /spl mu/s cycle refresh on 1Mb with SG mode.