A 1V supply 50nV//spl radic/Hz noise PSD CMOS amplifier using noise reduction technique of autozeroing and chopper stabilization

A low-noise CMOS amplifier operating at a low supply voltage is developed using the two noise reduction techniques of autozeroing and chopper stabilization. The proposed amplifier utilizes a feedback with virtual grounded input-switches and a multiple-output switched op-amp. The low-noise amplifier fabricated in a 0.18-/spl mu/m CMOS technology achieved 50-nV/VHz input noise at 1-MHz chopping and 0.5-mW power consumption at 1-V supply voltage.