Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond

Accelerated soft error testing with proton beam was performed for 65 nm CMOS latches for the first time. The soft-error rate (SER) dependence on the physical layout was clarified. SER has dependence on the size of the diffusion regions since critical charge and charge collection is strong function of them. By optimizing it, SER can be reduced by 70%. The scaling trend of SER was also investigated. It is shown that SER degradation due to scaling can be suppressed by the moderate reduction of the supply voltage.