Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274/spl mu/m2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.