Study on cobalt salicide on patterned wafers with 0.13/spl mu/m CMOS technology and below

In 0.11 /spl mu/m CMOS technology development, undesired cobalt salicide was found to be the cause of severe yield loss. Cobalt salicide was delaminated due to both the mechanical stress on active/shallow trench isolation (STI) and the improper cobalt salicidation. This paper presents detailed analysis of failure mechanism. X-ray diffraction (XRD) was used for the analysis of cobalt salicide on patterned wafers to determine whether the CoSi/sub 2/ phase is present or not. Our experimental results showed that this method could be used for the analysis of cobalt salicide on patterned wafers.