Clustering techniques for coarse-grained, antifuse FPGAs

In this paper, we present area and performance-driven clustering techniques for coarse-grained, antifuse-based FPGAs. A macro logic cell in this class of FPGAs has multiple inputs and multiple outputs. Starting with this macro cell a library of small logic cells can be generated and a target network was mapped with the library. For the minimum-area clustering, our algorithm minimizes the number of required macro logic cells to cover a network. Two linear equations were set up and we found the optimal mapping solution by using the equations. For the performance-driven clustering, the number of macro logic cells on the critical path is minimized by using the extension of Lawler's algorithm. The results show that the area-driven clustering algorithm reduced the number of macro logic cells by 12.29% and the performance-driven clustering reduced the maximum depth by 44.75% compared to a commercial tool.