VLSI architecture of low memory and high speed 2D lifting-based discrete wavelet transform for JPEG2000 applications

The paper presents a low memory and high speed VLSI architecture for 2D lifting-based lossless 5/3 filter discrete wavelet transform (DWT). The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity, transforming signal with extension, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operation of JPEG2000 and MPEG-4 applications. Basing on the proposed architecture, we designed and simulated a 2D DWT VLSI chip by 0.35 /spl mu/m 1P4M CMOS technology. The memory requirement of the N/spl times/N 2D DWT is N, and it can operate at 100 MHz clock frequency.