Design of a 2-GS/s 8-b self-calibrating ADC in 0.18 /spl mu/m CMOS technology

The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-/spl mu/m CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented.