A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit

This paper describes a fully differential DLL-based frequency multiplier using a noise-rejected voltage-controlled delay line (VCDL). In order to improve the power consumption and synthesized frequency range of the DLL-based frequency multiplier, we design an edge combiner using current mode logic to generate a fully differential output clock. This edge combiner consists of four stage fully differential current logic with XOR scheme. It can obtain the characteristic of high speed operation. Based on TSMC 0.18/spl mu/m 1P6M N-well CMOS process, the simulation results show that the DLL can operate from 360 to 550MHz. And, the frequency multiplier can synthesize frequency from 720MHz to 2.2GHz. The proposed frequency multiplier produces the 2/spl times/ and 4/spl times/ fully differential output clock frequency. The total power dissipation is only 38mW and the cycle-to-cycle jitter is less than 17ps.