A study on the implementation of the DSSS modem for a flight termination system

This paper describes the design of a direct sequence spread spectrum (DSSS) modem for a flight termination system using VHDL [R.K. Ducek, 2001] and FPGAs. The advantages of DSSS FTS includes the immunity from interference signals and anti-jamming effect. The error correcting scheme of a FTS uses (15,11) Reed-Solomon code. The spread codes of the inphase (I) and quadrature (Q) channel sequence can be generated using a gold sequence generator. The main algorithm is implemented in Altera APEX20K100E FPGAs