Designing a reorder buffer in Bluespec

Production capabilities for complex VLSI chips have outpaced the ability of current generation CAD tools to design and verify such chips effectively. Bluespec is designed to synthesize high-level descriptions in the form of guarded atomic actions into high quality structural RTL. While much work has been done on verifying both the correctness and synthesizability of Bluespec descriptions, the work on realistic large scale designs is in early stages. This paper explores the design of the reorder buffer for an out-of-order superscalar processor with a MIPS I ISA. We discuss the design methodologies which are suited for large scale Bluespec design and discuss some of the difficulties we encountered. Even though the work is still in progress, we show what level of performance is achievable under the current Bluespec compiler and what problems need to be solved to make the tool viable for commercial production environments.