Dual high-/spl kappa/ gate dielectric with poly gate electrode: HfSiON on nMOS and Al/sub 2/O/sub 3/ capping layer on pMOS

In this letter, a novel dual high-/spl kappa/ approach, different high-/spl kappa/ dielectrics in nMOS and pMOS, with poly Si gate electrode is introduced. By turning the Fermi-pinning effect into an advantage, this dual high-/spl kappa/ approach achieved a lower V/sub tp/ and a symmetrical V/sub tn//V/sub tp/ over a wide range of channel lengths for potential high-/spl kappa//poly Si CMOS application. In addition to the V/sub t/ control, this approach also can improve the drive current ratio between nMOS and pMOS, which would further scale the CMOS area by reducing the pMOS width.