A low power parallel architecture variable order B-spline interpolator for fractional sampling rate conversion

In this paper a sampling rate conversion system is discussed. The core of the system is developed using a B-Spline interpolation techniques. A 16 bit fixed point parallel architecture B-Spline basis generator has been designed exploiting the periodicity properly of the B-Spline basis functions. A mathematical analysis for reduced power consumption in the proposed parallel architecture has been discussed. Some further power reduction scheme has been provided using some very well known low power design techniques. A statistical measure of finite word length effect has been derived and computed. Also a reconfigurable and variable order B-Spline generator circuit is provided along with. Finally, Some modifications like folding have been employed in the variable order B-Spline generator to minimize the number of arithmetic processors.