A feedback concentrator for the Image Understanding Architecture

The Image Understanding Architecture (IUA) is a massively parallel, multilevel system. The hardware implementation of two important summary feedback mechanisms-some/none response and count responders-for the lower two processing levels of the first generation IUA are described. Both mechanisms are implemented using multiple copies of a single custom VLSI chip. A brief overview of the custom chip is provided. The performance of the IUA's low-level processor with the feedback concentrator is compared to a similar mesh-connected parallel processor without the feedback concentrator mechanism and is shown to be significantly faster. An overview of the plants for the feedback concentrator for the second generation IUA is provided.<
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