A failure analysis test structure for deep sub-micron CMOS copper interconnect technologies

Manufacturing yield and circuit reliability are becoming more and more dependent on interconnects (contacts, vias, and metal lines). These elements are therefore considered to represent one of the main limits to the future scaling down of integration processes. This paper presents a test structure, based on a suitable array of contacts and vias, which allows the contribution of interconnects to reliability and manufacturing yield degradation in new generation CMOS technologies to be evaluated. The test structure has been conceived to measure the statistical distribution of open failures in contacts and vias. In addition, it is possible to detect the physical location of interconnect faults, thus allowing a subsequent physical failure analysis. The test chip was integrated in 130 nm CMOS technology and experimentally evaluated.