Power delivery validation of processor front side bus

With lower I/O operating voltage and decreasing noise margin targets, it is imperative that the amount of noise generated on the voltage rails is kept within tight tolerances for high speed signaling. For this a good understanding of the behavioral model of the package and on-die passives is required in addition to the on-die transients generated on the power supply network when I/O's toggle. One of the major challenges is to accurately measure this dynamic power fluctuation (di/dt) for various I/O bit pattern excitation to understand the effectiveness of decoupling capacitors in the power distribution network. This paper discusses the power delivery validation methodology of the processor front side bus (FSB) that allows the user to input a stream of data into the I/O's to measure the power supply noise and the resulting dynamic power fluctuation. A detailed three dimensional model of the package, motherboard was then created and simulated using Speed2K/PowerSI by Sigrity Corporation to correlate with measured results.