Evaluation of silicon-on-sapphire enhancement JFETs for digital applications

Complete theoretical analysis of SOS n-channel JFET inverter, based on the exact I-V relationship and taking into account the changes in the electron mobility, is presented. A program to implement the analysis is also presented. The simulated results as compared with nMOS inverters resulted in 2.65%, 20% and 80% improvements in the logic swing, pull-up time and power dissipation respectively. A nine-stage ring oscillator is used to rate the performance of the enhancement SOS JFETs for digital applications.<
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