A methodology for evaluating the performance of RISC processors

A methodology is devised to simulate and evaluate the performance of RISC processors. The detailed model provides a way to evaluate the performance of the processor for various applications and under a wide spectrum of operation environments and conditions. The instruction flow of each instruction is modeled. The instruction requests the various units and stages of pipelines which are modeled as resources. The model is applied on the Motorola MC88100 RISC processor which includes four processing units and numerous pipelines to speed up the execution of instructions. From the model the processing speed is investigated for various applications, and the contention on some units is studied. Moreover, the utilization of units and mean waiting time are studied and discussed.<
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