Infrastructure for successful BEOL yield ramp, transfer to manufacturing, and DFM characterization at 65 nm and below

The challenges presented by deep-submicron interconnect back-end-of-line (BEOL) integration continue to grow in number, complexity, and required resolution at 90 nm and 65 nm. These challenges are causing industry-wide delays in technology deployment as well as low and often unstable yields. The historically observed improvements in time to successful yield ramp and final manufacturing yield as the industry deploys new technology nodes disappeared at 90 nm. Such improvements have been significant factors in fueling the semiconductor industry's growth. Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL - an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM.